1. Field of the Invention
The present invention is generally directed to a computer system and, more specifically, to a computer system comprising a host module and a plurality of client modules, each including one or more associated registers, that are accessible by a service processor.
2. Description of the Related Art
Serial buses have been widely implemented in conjunction with various hardware platforms. For example, the inter-integrated circuit (I2C) bus implements two bus lines, i.e., a serial data line (SDA) and a serial clock line (SCL). Each device that is connected to the I2C bus is software addressable by a unique address and a simple master/slave relationship exists between the devices. The I2C bus is a true multi-master bus that includes collision detection and arbitration to prevent data corruption, if two or more masters simultaneously initiate data transfer. Another example of a serial bus is the serial peripheral interface (SPI) bus, which in a simple embodiment is a four wire full duplex synchronous serial data link. The SPI bus has been utilized to connect peripherals to each other and to microprocessors. In general, the SPI bus is a three plus ‘n’ wire interface, where ‘n’ is the number of devices connected to the bus. In an SPI bus implementation, three wires carrying information between devices connected to the bus, i.e., two of the three lines of the bus transfer data (one line for each direction), and the third line is a serial clock. A dedicated select line is also typically implemented between a master and each slave.
Another serial bus that has been widely implemented in the automotive environment is the controller area network (CAN) bus, which implements relatively complex coded messages. All modules connected to the CAN bus utilize the same timing and participate in each communication. Similar to the I2C bus, the CAN bus utilizes resistors to pull the various bus lines to a resting state. The universal serial bus (USB) is a serial bus that has been widely implemented for connecting personal computers (PCs) to peripherals. The USB is a relatively complex bus that is focused on mass-market products, such as PCs. As another example of a serial bus, the IEEE 1394 bus has been widely utilized to link set-top boxes, digital versatile disks (DVDs) and digital televisions (TVs). The 1394 bus implements a pair of twisted wire pairs, one wire pair for data and the other wire pair for a clocking strobe.
Recently, at least one manufacturer has implemented service processors (SPs) in conjunction with a server system to control/monitor operation of system hardware modules, such as central processing units (CPUs) and application specific integrated circuits (ASICs), within the server system. In general, a SP initiates control and status checks to control and status registers (CSRs) located within one or more CPUs and/or ASICs. Typically, software running on a SP interacts with the system hardware through writing and reading the CSRs. In general, CSRs have been software accessible by the SP and hardware accessible by the system hardware. Typically, software writes to the CSRs and hardware reads the CSRs to configure hardware behavior and to initiate hardware processes. In a usual case, hardware writes to the CSRs to report status, including detected errors. The status is then read by the SP to determine the state of the hardware. In at least one SPARC® processor design, an address space identifier (ASI) bus has been utilized by an SP to access CSRs of hardware modules to, for example, diagnose module associated problems.
SPARC architecture based processors are available from Sun Microsystems, Inc., Palo Alto, Calif. SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc.
As noted above, SPs have accessed CSR registers via the ASI bus. Unfortunately, when a SP accesses CSRs through the ASI bus, the SP may not be provided access to the CSRs within a desired time frame. This is due to the fact that other processes may be utilizing the ASI bus when the SP desires access to a CSR. Furthermore, modules that include CSRs may operate at different clock frequencies, which complicates the reading/writing of CSRs by an SP.
What is needed is a reliable technique for providing service processor (SP) access to control and status registers (CSRs) of different hardware modules within a predetermined time period. It would also be desirable if the technique readily facilitated access to hardware modules that operate at different clock frequencies.